This invention is in the field of integrated circuits, and is more specifically directed to interconnection systems and materials used therein.
Over recent years, many important advances have been made in the manufacture of integrated circuits, particularly in reducing the chip area required for the implementation of circuit elements. These advances include reduction in the critical dimensions of active elements such as transistors and interconnections, and the use of multiple interconnection layers in each integrated circuit. These advances have greatly increased the number of transistors that may be implemented in a given area, and thus greatly increased the functionality and performance of conventional integrated circuits, as well as reducing the manufacturing cost for such functionality.
However, the implementation of multiple interconnection layers introduces significant complexity in the design, layout, and manufacture of the integrated circuits, particularly as the feature sizes of the interconnections have become smaller, even into the submicron range. For example, modern integrated circuits such as high-density dynamic random access memories (DRAMs) may have on the order of five levels of interconnections; the formation and patterning of these multiple levels, as well as the provision of contacts among these levels of interconnections and contacts from interconnection levels to active devices (including the bulk silicon), can therefore become quite complex. Furthermore, as interconnect feature sizes become very small, the conductivity of individual interconnections becomes a concern, and as such the selection of the appropriate material for individual interconnection layers can become a relatively complex decision. Additional complications in the implementation of such interconnection layers also result from processing considerations, particularly where the integrated circuit wafers must be subjected to high temperature processing at a point in the manufacturing flow after the deposition and patterning of one or more of the interconnection layers.
An example of a conventional DRAM device constructed according to complementary metal-oxide-semiconductor (CMOS) technology, and illustrating multiple interconnection layers, is illustrated in FIGS. 1 and 2. FIG. 1 illustrates two portions of partially-fabricated integrated circuit 20, namely array portion 20a and periphery portion 20p formed at a surface of p-type substrate 2. Specifically, periphery portion 20p as shown in FIG. 1 includes a p-channel transistor having source/drain regions 6 formed within n-well 4, at locations defined by field oxide structures 5 and gate structure 8; gate structure 8 is vertically separated from the channel region between source/drain regions 6 by a gate dielectric, in the conventional manner. Gate structures 8 may be encapsulated, as shown in FIG. 1, to permit contacts for subsequent interconnection layers to be made in a self-aligned manner relative to gate structures 8, without shorting thereto. Of course, n-channel periphery transistors will also be implemented in periphery portion 20p, within a p-type well, but are not shown in FIGS. 1 and 2 for the sake of clarity.
In this example, insulating material 10 collectively refers to multiple insulating layers, which may include a barrier layer, a doped oxide (BPSG) layer and additional insulating layers that overlie gate structure 10. First-level metal conductor 22 makes contact to one of source/drain regions 6, through a contact opening etched through overlying insulating material 10 at that location. Additional metallization layers, such as second-level metal 24 and third-level metal 26 are similarly formed in periphery portion 20p as shown in FIG. 1, physically and electrically insulated from one another by additional levels of insulating material 10 with vias therethrough for purposes of electrical connection.
Array portion 20a of integrated circuit 20 contains, in the portion illustrated in FIG. 2a, two storage capacitors which are formed in a "crown" fashion, as described in further detail in commonly assigned copending application Ser. No. 08/845,755, filed Apr. 25, 1997, entitled "A Silicon Nitride Sidewall and Top Surface Layer Separating Conductors", incorporated hereinabove by reference. In this example, the storage capacitors are formed by field plate 18 that is electrically coupled to a fixed voltage, and separated from individual second plates 16 by capacitor dielectric layer 17. Each of plates 16, 18 is preferably formed of polysilicon, while capacitor dielectric layer 17 may be formed of silicon dioxide, of silicon nitride, or of a sandwich structure of silicon dioxide and silicon nitride, as known in the DRAM art. Plates 16 are respectively connected to polysilicon plugs 12 and thus to n-type source drain regions 7 at the surface of p-type well 9; the location of which are defined by field oxide structures 5 and gate structures 8. Well 9 is formed within deep n-type well 3, at a surface of p-type substrate 2.
Bit line 15 also extends laterally above gate structures 8 and field oxide structures 5, separated therefrom by one of the layers of insulating material 10, while gate structures 8 for some distance along array portion 20a, perpendicularly relative to bit line 15, to control connection of the storage capacitors to their respective bit lines, in the usual manner for DRAMs. As shown in FIGS. 1 and 2, bit line 15 makes contact to source/drain regions 7 both directly and indirectly. Within array portion 20a, between adjacent storage cells, bit line 15 extends into and through a bit line contact BLC (FIG. 2) to make contact to source/drain region 7. Away from the storage cells, first level metallization layer 22 is also provided to strap bit line 15 to another source/drain region 7. Second-level metal layer 24 and third-level metal layer 26 are also provided in array portion 20a, to provide interconnection among the various circuit elements.
As is evident from FIGS. 1 and 2, bit line 15 is formed prior to the formation of capacitor plates 16, 18, and as such must have sufficient thermal stability to be able to withstand the temperature sequence used in the formation of plates 16, 18, as well as capacitor dielectric 17 therebetween. Accordingly, in this conventional arrangement of FIGS. 1 and 2, bit line 15 must be formed of a material that can withstand such processing. One particular example of such material is silicide-clad polysilicon, such as tungsten polycide. Alternatively, a multi-layer structure of n+ doped polysilicon (when contacting n-type source/drain regions as illustrated in FIGS. 1 and 2) stacked with tungsten disilicide may also be used. These materials differ quite radically from conventional aluminum metallization as used in metal layers 22, 24, 26, as such metallization is not able to withstand processing temperatures above 450.degree. C., and as such cannot withstand the processing required to form capacitor plates 16, 18 and capacitor dielectric 17.
However, these materials are not suitable for use as a first level metal interconnection layer in periphery portion 20p, or even within array portion 20a, due to the relatively high contact resistance provided by these materials, and also because these materials do not present a barrier to the diffusion of dopant (of either n-type or p-type) or of silicon therethrough. As a result, first level metal layer 22 is necessary in the conventional DRAM integrated circuit structure of FIGS. 1 and 2 to provide interconnection to elements in periphery portion 20p, and as a strap connection from bit line 15 to source/drain region 7 as shown.
As is evident from the conventional arrangement of FIGS. 1 and 2, the interconnections are quite complex in this DRAM device. Specifically, five interconnection layers are present in this conventional arrangement, three of which are metal, plus bit line 15 and gate structures 8. As such, this structure involves significant manufacturing cost and yield risk from each of these interconnection levels. Furthermore, in the case where bit line 15 is formed of doped polysilicon, connection of bit line 15 to p-type doped regions 6 is not possible, due to the counterdoping effects.
By way of further background, titanium nitride is a known conductive material in the field of integrated circuits. The formation of local interconnections from titanium nitride for active transistor elements as a by-product of direct react silicidation is described in U.S. Pat. No. 4,676,866, U.S. Pat. No. 4,804,636, and U.S. Pat. No. 5,302,539, each commonly assigned herewith and incorporated by reference hereinto. The use of deposited titanium nitride as a gate electrode is described in U.S. Pat. No. 4,605,947. The use of titanium nitride as a barrier layer or adhesion layer (or both) in a multiple-level metallization layer is disclosed in Travis, et al., "A Scalable Submicron Contact Technology Using Conformal LPCVD TiN", International Electron Device Meeting (IEEE, 1990), pp. 47-50; Kikkawa, et al., "A quarter-micron interconnection technology using Al--Si--Cu/TiN alternated layers", International Electron Device Meeting (IEEE, 1991), pp. 281-284. Use of titanium nitride adhesion or barrier layers in DRAM devices is described in Nakamura, et al. "Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFET's and capacitors by using bonded SOI technology--Reversed-Stacked-Capacitor (RSTC) Cell", International Electron Device Meeting (IEEE, 1995), pp. 889-892; Lee, et al. "Simultaneously Formed Storage Node Condact and Metal Contract Cell (SSMC) for 1 Gb DRAM and Beyond", International Electron Device Meeting (IEEE, 1996), pp. 593-596, and in Byun, et al. "W as a BIT Line Interconnection in COB Structured DRAM and Feasible Diffusion Barrier Layer", Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials (Osaka, Japan, 1995), pp. 75-81.